The development of novel microelectronic devices as well as the scaling of existing devices concepts is tightly linked to the availability of mature and reliable integration of new dielectrics. On the nanometer scale those materials act as gate insulator, stress or strain layers or memory dielectrics. NaMLab performs electrical stress measurements on a large variety of devices to assess the reliability of the used dielectric materials. Moreover, simulation and modeling of the different degradation effects give deeper insight into the physical mechanisms. The results of the spatial localization of different defect sites within the devices provides an informative base to our partners for the optimization of manufacturing processes or device structures while targeting at further improved reliability.
In face of the increasing complexity of power devices or high performance logic devices any compromise in reliability is not acceptable. Especially for high dielectric constant gate insulators, the fundamental understanding of bias temperature instability (BTI), hot carrier injection (HCI), stress induced leakage currents (SILC), and time dependent dielectric breakdown (TDDB) are of major interest. To further deepen the understanding of use-case realistic stress conditions we put additional focus on the assessment of circuit reliability. That is, besides the standard reliability tests on single devices that are typically performed with high statistics at our partners premises, more advanced and time consuming characterization methods are investigated at NaMLab.
Fig. 1 depicts the schematic of a ring-oscillator circuit where stress conditions switch between BTI, HCI and an off-state stress at high frequencies close to use-conditions. Our measurement results show, that the off-state stress occurring at the drain-side of the transistors (when the gate voltage is low while drain voltage is high) leads to a modified degradation mechanism. The reason behind asymmetric device degradation is a negative field peak at the drain-sided channel edge (see Fig. 2). The trapping induced by this field peak induces a local threshold voltage shift at the drain side counteracting the BTI degradation in the on-state. Consequently, the measured frequency degradation in the ring oscillator is lower than extrapolated by pure DC BTI stress analysis.
Fig. 1 Schematic of ring oscillator test structure and voltage evolution during dynamic stress indicating the off-state stress condition. 
Fig. 2: TCAD simulation of the electric field distribution within a 22nm
FDSOI transistor under off-state stress condition. Field peaks at the drain-side during off-state stress can lead to asymmetric device degradation.
The growing interest in high speed and RF technologies assert for the importance of reliability characterization beyond the conventional DC or AC methodology. Power amplifiers for example that are adopted to realize on-chip transmitters have to operate stable at frequencies well beyond the GHz range. Thus, the correct understanding of degradation mechanisms that affect the RF device parameters becomes increasingly important. The data shown in Fig. 3 reveal changes in the effective gate to drain and gate to source capacitance (Cgd, Cgs) that is caused by an asymmetric threshold voltage shift under HCI stress conditions.
